In advanced integrated circuit (IC) processes, passive elements (more particularly, capacitors) are very likely to have mismatches when the capacitors are not small. This results in poor performance (e.g. poor resolution) for circuitries which require fine accuracy, especially for analog-to-digital converters (ADC) comprising capacitor-based digital-to-analog converters (DAC) such as a successive approximation register (SAR) ADC. Therefore, a calibration mechanism for an ADC which can calibrate the mismatch caused by capacitor to achieve high resolution is extremely desirable in the art.